1. Field of the Invention
The present invention relates to a field effect transistor, and more particularly, it relates to a field effect transistor with a high withstand voltage and a low resistance.
2. Description of the Related Art
Conventionally, a field effect transistor in which a current flows in the direction of the thickness of a substrate has been used as a current control element.
Referring now to FIG. 26, a reference numeral 105 denotes one example of a conventional type of a field effect transistor, and it has a single crystal silicon substrate 111. On the surface of the single crystal substrate 111, a drain region 112 formed by epitaxial growth is disposed.
Within the single crystal silicon substrate 111, N-type impurities are doped to a high concentration and a drain electrode film 148 is formed on the backside thereof. Within the drain region 112, N-type impurities are doped to a low concentration, and a P-type base region 154 is formed in the vicinity of the surface thereof.
Within the base region 154, N-type impurities are further diffused from the surface to form a source region 161.
A reference numeral 110 denotes a channel region located between the edge portion of the source region 161 and the edge portion of the base region 154. On tip of the channel region 110, a gate insulation film 126 and a gate electrode film 127 are disposed in this order.
On the surface and the sides of the gate electrode film 127, an interlayer insulation film 141 is formed, and a source electrode film 144 is formed on the surface thereof.
The base regions 154 as described above are disposed in islands in the vicinity of the surface of the drain region 112, and one base region 154, and the source region 161 and the channel region 110 disposed within the base region 154 form one cell 101.
FIG. 27 is a plan view showing the surface of the drain region 112, wherein a plurality of rectangular cells 101 are arranged in matrix.
In the case where the field effect transistor 105 is used, when the source electrode film 144 is set at a ground potential, a positive voltage is applied to the drain electrode film 148, and a gate voltage (positive voltage) of equal to or greater than the threshold voltage is applied to the gate electrode film 127, an N-type inversion layer is formed on the surface of the P-type channel region 110 so that the source region 161 and the drain region 112 are connected to each other through the inversion layer, thereby rendering the field effect transistor 105 conductive.
When a voltage of equal to or smaller than the threshold voltage (e.g., ground voltage) is applied to the gate electrode film 127 from such a state, the inversion layer disappears so that the field effect transistor 105 is cut off.
However, when a large number of the cells 101 as described above are arranged, an attempt to increase the withstand voltage requires a decrease in the distance between the cells 101, and hence the gate electrode width is decreased, thereby resulting in an increase in conduction resistance.
Further, the withstand voltage is determined by the corner portion of the cell 101, and hence there is still a problem in that even if the distance between the cells 101 is decreased, the withstand voltage is not so improved as expected.
The present invention has been made in order to solve the foregoing deficiencies in the prior art. It is therefore an object of the present invention to provide a high withstand voltage and low resistance field effect transistor.
For solving the foregoing problem, a first aspect of the present invention is a field effect transistor, comprising: a main diffused region of a second conductivity type formed within a high resistance layer of a first conductivity type, and disposed on the surface side of the high resistance layer; a source region of the first conductivity type formed within the main diffused region, and disposed on the surface thereof; a ring-shaped channel region being formed in a ring, being a part of the main diffused region, and located between the edge of the main diffused region and the edge of the source region; a drain region surrounded by the ring-shaped channel region; a gate insulation film disposed at least on the channel region surface; and a gate electrode film disposed on the gate insulation film surface, the source region is located at an outer periphery of the ring-shaped channel region, the source region and the high resistance region being electrically connected with each other upon inversion of the channel region surface into the first conductivity type due to a voltage applied to the gate electrode film.
A second aspect of the present invention is the field effect transistor in accordance with the first aspect of the present invention, wherein the drain region surrounded by the ring-shaped channel region has at least one narrow elongate body portion, and a plurality of branch portions with their respective one ends connected to the body portion, and the ring-shaped channel region is disposed so as to surround the periphery of the body portion and the branch portions.
A third aspect of the present invention is the field effect transistor in accordance with the second aspect of the present invention, wherein the body portion located between the branch portions extends roundly toward the inside of the body portion itself.
A fourth aspect of the present invention is the field effect transistor in accordance with the third aspect of the present invention, wherein the channel region at each tip of the branch portions is configured with three sides intersecting with each other at substantially right angles.
A fifth aspect of the present invention is the field effect transistor in accordance with the third aspect of the present invention, wherein the main diffused region comprises a P-type base region and a P-type ohmic region having a deeper diffusion depth than that of the base region, a conductive layer of the first conductivity type with a lower resistance than that of the high resistance layer is disposed in the vicinity of the surface inside of the drain region, a pn junction is formed with the ohmic region and the conductive region at least on the surface of the tip portion of the portion extending roundly toward the inside of the body portion.
A sixth aspect of the present invention is the field effect transistor in accordance with the second aspects of the present invention, wherein a conductive layer of the first conductivity type with a lower resistance than that of the high resistance layer is disposed on the surface side of the inside of the drain region.
A seventh aspect of the present invention is the field effect transistor in accordance with the third aspect of the present invention, wherein a conductive layer of the first conductivity type with a lower resistance than that of the high resistance layer is disposed in each of the branch portions.
An eighth aspect of the present invention is the field effect transistor in accordance with the second aspect of the present invention, wherein a floating potential region of the second conductivity type not in contact with the channel region is disposed on the surface side of the inside of the drain region.
A ninth aspect of the present invention is the field effect transistor in accordance with the first aspect of the present invention, wherein the high resistance layer is disposed on a low resistance layer of the first conductivity type with a lower resistance than that of the high resistance layer, and a drain electrode film for forming an ohmic junction with the low resistance layer is disposed on the back side of the low resistance layer.
A tenth aspect of the present invention is the field effect transistor in accordance with the first aspect of the present invention, wherein an anode electrode film for forming a Schottky junction with the high resistance layer is disposed on the back side of the high resistance layer, such that a diode in which the anode electrode film is taken as an anode, and the high resistance layer is taken as a cathode is formed.
An eleventh aspect of the present invention is the field effect transistor in accordance with the first aspect of the present invention, wherein the high resistance layer is disposed on a collector layer of the second conductivity type, and a collector electrode film for forming an ohmic junction with the collector layer is disposed on the back side of the collector layer.
FIGS. 1(a) to 1(c) are views for illustrating the manufacturing process of a field effect transistor of one example of the present invention;
FIGS. 2(a) to 2(c) are views for illustrating the manufacturing process of the field effect transistor of the one example of the present invention;
FIGS. 3(a) to 3(c) are views for illustrating the manufacturing process of the field effect transistor of the one example of the present invention;
FIGS. 4(a) to 4(c) are views for illustrating the manufacturing process of the field effect transistor of the one example of the present invention;
FIGS. 5(a) and 5(b) are views for illustrating the manufacturing process of the field effect transistor of the one example of the present invention;
FIGS. 6(a) and 6(b) are views for illustrating the manufacturing process of the field effect transistor of the one example of the present invention;
FIGS. 7(a) and 7(b) are views for illustrating the manufacturing process of the field effect transistor of the one example of the present invention;
FIGS. 8(a) and 8(b) are views for illustrating the manufacturing process of the field effect transistor of the one example of the present invention;
FIGS. 9(a) to 9(c) are views for illustrating the manufacturing process of the field effect transistor of the one example of the present invention;
FIGS. 10(a) to 10(c) are views for illustrating the manufacturing process of the field effect transistor of the one example of the present invention;
FIGS. 11(a) and 11(b) are views for illustrating the manufacturing process of the field effect transistor of the one example of the present invention;
FIGS. 12(a) to 12(c) are views for illustrating the manufacturing process of the field effect transistor of the one example of the present invention;
FIGS. 13(a) and 13(b) are views for illustrating the manufacturing process of the field effect transistor of the one example of the present invention;
FIGS. 14(a) and 14(b) are views for illustrating the manufacturing process of the field effect transistor of the one example of the present invention;
FIGS. 15(a) and 15(b) are views for illustrating the manufacturing process of the field effect transistor of the one example of the present invention;
FIG. 16 is a view for illustrating the manufacturing process of the field effect transistor of the one example of the present invention;
FIGS. 17(a) and 17(b) are cross sectional views of FIG. 16, for illustrating the manufacturing process of the field effect transistor of the one example of the present invention;
FIG. 18 is a view for illustrating the manufacturing process of the field effect transistor of the one example of the present invention;
FIGS. 19(a) and 19(b) are cross sectional views of FIG. 18, for illustrating the manufacturing process of the field effect transistor of the one example of the present invention;
FIGS. 20(a) and 20(b) are views for illustrating the manufacturing process of the field effect transistor of the one example of the present invention;
FIGS. 21(a) and 21(b) are views for illustrating the positional relationship among a conductive layer, a channel region, and a source region, and a fragmentary view thereof on an enlarged scale for illustrating the position of a floating potential region, respectively;
FIG. 22 is a view for illustrating the condition where the conductive layer has been partially formed within a drain region;
FIG. 23 is a view showing an example of the plan configuration of the channel region and a diffusion layer inside thereof of the field effect transistor of the present invention;
FIG. 24 is a view showing an example of the plan configuration of the channel region and the diffusion layer inside thereof of the field effect transistor of the present invention;
FIGS. 25(a) and 25(b) are views for illustrating an IGBT type field effect transistor using a Schottky junction of another example of the present invention, and a view for illustrating an IGBT type field effect transistor using a pn junction of a still other example of the present invention, respectively;
FIG. 26 is a view for illustrating a prior-art field effect transistor;
FIG. 27 is a view for illustrating the arrangement of cells of the field effect transistor;
FIG. 28 is a view for illustrating a pattern among patterns of the field effect transistor of the present invention where a part of the ohmic region is extends toward inside of N-type region;
FIG. 29 is a view for illustrating the ohmic region in the pattern;
FIG. 30 is a view for illustrating the channel region in the pattern;
FIG. 31 is a view for illustrating the source region in the pattern;
FIG. 32 is a view for illustrating a pattern among patterens of the field effective transistor of the present invention where a part of the ohmic region is gradually extending toward inside of N-type region;
FIG. 33 is a view for illustrating the ohmic region in the pattern;
FIGS. 34(a) to 34(c) are views for illustrating a manufacturing process of the field effect transistor wherin a part of the ohmic region extends toward inside of N-type region;
FIGS. 35(a) to 35(c) are views for illustrating the subsequent process;
FIGS. 36(a) to 36(c) are views for illustrating the subsequent process;
FIGS. 37(a) to 37(c) are views for illustrating the subsequent process;
FIGS. 38(a) to 38(c) are views for illustrating the subsequent process;
FIGS. 39(a) to 39(c) are views for illustrating the subsequent process;
FIGS. 40(a) to 40(c) are cross sectional views for illustrating a manufacturing processes of the pattern where a part of the ohmic region gradually extends toward inside of N-type region and are showing a tip portion, a middle portion, and a root portion, respectively;
FIGS. 41(a) to 41(c) are cross sectional views for illustrating the pattern where a part of the ohmic region gradually extends toward inside of N-type region and are showing a tip portion, a middle portion, and a root portion, respectively;
FIG. 42 is a view illustrating another plan pattern of the present invention;
FIGS. 43(a) and 43(b) are views illustrating manufacturing processes of the swelling portion of the FIG. 42; and
FIGS. 44(a) and 44(b) are cross sectional views of FIG. 42.